1. Field of the Invention
The present invention relates to a ferroelectric memory and its method of operation, more particularly to the circuit structure of a ferroelectric memory and a method of reading data from a ferroelectric memory.
2. Description of the Related Art
Ferroelectric memory stores data in ferroelectric capacitors, which have an intrinsically bistable charge polarization, providing the advantage of nonvolatile data retention combined with comparatively rapid, low-voltage write access. Conventional ferroelectric memories include the 2T2C type that uses two transistors and two oppositely polarized capacitors to store one bit of data, and the 1T1C type that uses one transistor and one capacitor per bit. The 1T1C type is preferable for high-density memory designs.
A memory cell in a 1T1C ferroelectric memory is read by transferring charge between the ferroelectric capacitor and a bit line, and comparing the resulting bit-line potential with a reference potential. Normally, the reference potential is produced on another bit line, by a reference cell or dummy cell connected to the other bit line, but there are problems with this scheme. If the reference cell includes a conventional (paraelectric) capacitor, the reference potential may be inaccurate. If the reference cell includes a ferroelectric capacitor, it degrades more quickly than the ferroelectric capacitors in the data memory cells, because of the large number of times the reference cell is read, severely shortening the life of the memory device.
A type of 1T1C ferroelectric memory from which data can be read without reference cells has been proposed in, for example, U.S. Pat. No. 6,363,002 (and a corresponding Japanese Unexamined Patent Application Publication, No. 11-260066). In this memory, an unselected bit line is used as a reference. A read operation is carried out by supplying two opposed pulses: the first pulse elicits a data-dependent signal from the selected memory cell; the second pulse restores the selected bit line to a level for which the direct-current bias voltage on the unselected bit line is an optimal reference potential. A disadvantage of this scheme is that the reference potential depends on the bit-line capacitance, and extra current is consumed in biasing the unselected bit line.